1. Field of the Invention
The present invention relates to a semiconductor device and a logic circuit, and more particularly, it relates to a logic gate by BiCMOS.
2. Description of the Background Art
FIG. 12 is a circuit diagram showing a conventional BiCMOS inverter. A P-channel MOSFET 1 has a drain which is connected to a node 7, a gate which is connected to an input node 6, and a source which is connected to a high potential point 8 respectively. An N-channel MOSFET 2 has a drain which is connected to the node 7, a gate which is connected to the input node 6, and a source which is connected to a low potential point 40 (ground in this case) respectively. Therefore, the P-channel MOSFET 1 and the N-channel MOSFET 2 form a CMOS inverter, which inverts a logic (hereinafter referred to as "input logic") inputted in the input node 6 and supplies the same to the node 7.
An NPN transistor 3 has a collector which is connected to the high potential point 8, a base which is connected to the node 7, and an emitter which is connected to an output node 9 respectively. A PNP transistor 4 has a collector which is connected to the low potential point 40, a base which is connected to the node 7, and an emitter which is connected to the output node 9 respectively. A resistor 5 is connected between the output node 9 and the node 7. The structure of such an inverter is described in Denshi Joho Tsushin Gakkai Ronbun-shi Vol. J73-C-II, No. 12, 1990, p. 869, for example.
The operation of the inverter having the aforementioned structure is now described. It is assumed that the high potential point 8 is supplied with a potential of 5 V, while a high level of the input logic is 5 V and a low level thereof is 0 V.
When the input logic is at a high level (5 V), the P-channel MOSFET 1 enters an OFF state and the N-channel MOSFET 2 enters an ON state, whereby the potential at the node 7 is 0 V. When a transient state as described below is completed and the circuit enters a stationary state with no current flowing to the resistor 5, the potential of the output node 9 becomes equal to that of the node 7. Namely, the output node 9 outputs 0 V (low level), to provide an output obtained by inverting the input logic.
When the input logic is converted from the high level to a low level after such a stationary state, the P-channel MOSFET 1 first enters an ON state and then the N-channel MOSFET 2 enters an OFF state. Therefore, a current flows from the high potential point 8 to the node 7 through the P-channel MOSFET 1, to raise up the potential of the node 7. Since the potential of such a node 7 is generally changed at an extremely high speed (less than 1 ns), it is possible to raise up the same before the potential of the output node 9 is increased by setting the resistor 5 at a high resistance value to some degree. Thus, the potential of the node 7 is increased with respect to the output node 9.
Assuming that each of the NPN transistor 3 and the PNP transistor 4 has a base-to-emitter forward junction voltage V.sub.BE of 0.7 V, the NPN transistor 3 enters an ON state when potential difference between the node 7 and the output node 9 exceeds 0.7 V. Then, the potential of the output node 9 is rapidly raised up by a current which flows from the high potential point 8 to the output node 9 through the NPN transistor 3. However, the potential of the node 7 being increased only up to 5 V, that of the node 9 is merely raised to: EQU 5(V)-0.7(V)=4.3(V) (1)
by the current flowing through the NPN transistor 3. Thereafter the potential of the output node 9 is increased from 4.3 V to 5 V by a current which flows to the output node 9 through the P-channel MOSFET 1 and the resistor 5, and then the circuit enters a stationary state. The NPN transistor 3 is in an OFF state at this time.
As the resistance value of the resistor 5 is reduced, the current flowing to the output node 9 through the resistor 5 is increased to quickly raise up the potential of the output node 9. However, the value of the resistor 5 cannot be excessively reduced, since the base-to-emitter voltage V.sub.BE of the NPN transistor 3 must be maintained at 0.7 V. Therefore, the potential of the output node 9 is changed from 4.3 V to 5 V at a lower speed as compared with that for the increase from 0 V to 4.3 V.
While the potential of the output node 9 is raised up from the low level (0 V) to the high level (5 V), the PNP transistor 4 is regularly maintained in an OFF state and exerts no influence on the potential of the output node 9 since the potential of its base, i.e., the potential of the node 7 is higher than the potential (0 V) of its emitter.
When the input logic is converted from a low level (0 V) to a high level (5 V) in a stationary state, on the other hand, the N-channel MOSFET 2 and the PNP transistor 4 perform operations corresponding to the aforementioned operations of the P-channel MOSFET 1 and the NPN transistor 3 respectively, whereby the potential of the output node 9 is reduced from 5 V to 0.7 V and then loosely reduced further to 0 V.
Thus, it is understood that the BiCMOS inverter shown in FIG. 12 is the so-called full-swing inverter, which swings over the full range of 0 V to 5 V.
In such a structure, however, a load carrying capacitance which is caused by base capacitances of the NPN transistor 3 and the PNP transistor 4 is large enough to reduce the speed of the potential change of the node 7, since the node 7 is connected to the bases of the transistors 3 and 4. The potential of the output node 9 follows potential increase (or decrease) of the node 7 when the same is raised from 0 V up to 4.3 V (or reduced from 5 V to 0.7 V), and hence the change, i.e., the change of the outputted logic level, is also reduced in speed.